The design of a new ternary cpu architecture and the pitfalls we came across when creating that design. How the huge amount of binary tools simply are not good enough to do the job and how we had to create a new toolset and workflow from the ground up. How the lack of actual ternary hardware to work on led to a failed chip from MOSIS that was largely unstable. How this was addressed so that it does not reoccur. And talk about the sleepless nights that ended with yelling Eureka and success